1. Field of Endeavor
The example embodiments relate to methods for manufacturing semiconductor devices, and more particularly, to methods for manufacturing semiconductor devices including fin-type channel regions.
2. Related Art
As the integration density of semiconductor devices increases, the surface area available for forming conventional metal-oxide-semiconductor field effect transistor (MOSFET) is reduced correspondingly. For semiconductor devices utilizing conventional planar transistors, higher integration densities also lead to corresponding reductions in the channel lengths of the transistors utilized in such devices. The reduction in the channel lengths will tend to result in improvements in some parametric and/or operating characteristics of the resulting devices, for example, increased operating speed.
Reducing the channel length of planar transistors to levels below about 100 nm, however, also tends to degrade other parametric and/or operating characteristics of the resulting devices. One particular issue associated with short channel devices include increased leakage as a result of the decreased distance between the corresponding source and drain regions provided on opposite sides of the gate electrode. One approach for addressing these issues involves increasing the doping level of the channel regions, but, while tending to reduce leakage, the increased doping tends to degrade the active switching function of the transistor. As a result, the overall performance of the resulting MOSFET device may be severely degraded by these short channel effects (SCE) resulting, for example, in increased leakage currents and less stable and uniform sub-threshold voltages.
One approach for addressing the SCE problem in MOSFET devices involves the fabrication of a double gate field effect transistor having a non-planar channel structure with two gates formed on opposite faces of the non-planarized channel. Double gate field effect transistors fabricated in this manner tend to exhibit an improved channel control capability that is attributed, at least in part, to controlling the channel with two gates, thereby reducing the SCE problem. Further, when the voltages applied to the gate electrodes of a double gate field effect transistor are sufficient to place the transistor in an “on” state, an inversion layer will extend from each surface of the non-planar channel controlled by the gate electrodes and will tend to increase the “on” current levels, Ion, that can be achieved relative to a conventional planar transistor formed in the same surface area.
Field effect transistors have been manufactured with fin channel structures (hereinafter, referred to as finFETs) for improving certain device performance parameters in the resulting semiconductor devices. One example of a semiconductor device utilizing a finFET structure includes a double gate field effect transistor which may be fabricated using a method whereby active regions (which are also referred to, in some instances, as fin structures) are formed by etching a semiconductor substrate using a hard mask, filling the resulting recesses with an insulating material such as silicon oxide, exposing portions of the vertical and horizontal surfaces of the active regions, forming a gate dielectric film, for example, a thin oxide, on the exposed surfaces of the active regions, and forming a gate electrode on the gate dielectric film, thereby providing additional control over the threshold voltage of the resulting transistors.
Another example of a finFET device encompasses integrated circuit field effect transistor devices including a substrate that includes a primary surface and an active channel pattern formed on the primary surface. This active channel pattern may include a series of stacked channels that are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode is then formed on the exposed surfaces of the channels, including that portion of the exposed surfaces that extend through the at least one tunnel.
Because the top surfaces and side surfaces of the fins in a finFET can be used as channel regions, finFETs can provide wider effective channel regions than conventional planar transistors that could formed in the same surface area of the substrate. Accordingly, finFETs can provide increased operation current, thereby providing improved performance relative to corresponding planar transistors and/or increased integration density while still maintaining acceptable parametric and performance characteristics.
Many conventional finFETs are fabricated using silicon-on-insulator (SOI) substrates in which the fin structures are electrically insulated from the bulk substrate bodies. Accordingly, the threshold voltage of such finFET transistors cannot be effectively controlled using body-bias, thereby complicating efforts to control the threshold voltage of the resulting CMOS transistors. However, if a conventional bulk substrate is used to allow for more effective body-bias control, the resulting increase in the extent of the drain depletion region tends to increase a junction leakage current, off current, and junction capacitance, thereby degrading the performance of the semiconductor devices. In addition, in highly integrated devices, there tend to be additional decreases in threshold voltage and corresponding increases in off current as a result of short channel effects.
Another problem associated with finFETs is high contact resistance. For example, conventional finFET structures may include bit line contacts formed across and contacting the top surfaces of the fins. However, because the bit lines contact only the narrow top surfaces of the fins, the resistance of these bit line contacts may be increased to a level that will tend to degrade the performance of the resulting devices. The configuration of the fins may be modified in order to increase the area available for forming the bit line contacts and reduce the contact resistance. Reconfiguring the fin structure to provide additional contact area, however, tends to increase the complexity of the semiconductor device fabrication and/or reduce the degree of integration density that can be achieved, thereby increasing costs and tending to suppress yield.
According to some conventional teachings, the sizing of the source and drain regions in contact with fins may be increased to provide greater contact area. However, as the distance between the fins is increased to accommodate the enlarged source and drain regions, the overall degree of integration that can be achieved in the resulting finFET device will be reduced.
Another problem associated with fabricating finFETs is damage to and/or collapse of the thin fins protruding from a substrate. The likelihood of such damage or collapse increases as the widths of the fins is reduced. For example, elongated fins projecting from the substrate according to conventional processes are not initially provided with any supporting or reinforcing structures. Accordingly, forming the fins in such a manner results in fin structures exhibiting increased susceptibility to mechanical damage and which may result in the collapse or damage to the fin structures during subsequent fabricating processes.